Freescale Semiconductor /MKL36Z4 /LCD /GCR

LCD duty select

0 (000): Use 1 BP (1/1 duty cycle).

1 (001): Use 2 BP (1/2 duty cycle).

2 (010): Use 3 BP (1/3 duty cycle).

3 (011): Use 4 BP (1/4 duty cycle). (Default)

7 (111): Use 8 BP (1/8 duty cycle).

LCD Clock Prescaler

LCD Clock Source Select

0 (0): Selects the default clock as the LCD clock source.

1 (1): Selects output of the alternate clock source selection (see ALTSOURCE) as the LCD clock source.

LCD Driver Enable

0 (0): All front plane and back plane pins are disabled. The LCD controller system is also disabled, and all LCD waveform generation clocks are stopped. V LL3 is connected to V DD internally. All LCD pins, LCD_Pn, enabled using the LCD Pin Enable register, output a low value.

1 (1): LCD controller driver system is enabled, and front plane and back plane waveforms are generated. All LCD pins, LCD_Pn, enabled if PAD_SAFE is clearusing the LCD Pin Enable register, output an LCD driver waveform. The back plane pins output an LCD driver back plane waveform based on the settings of DUTY[2:0]. Charge pump or resistor bias is enabled.

LCD Stop

0 (0): Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Stop mode.

1 (1): Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Stop mode.

LCD Doze enable

0 (0): Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Doze mode.

1 (1): Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Doze mode.

Fast Frame Rate Select

0 (0): Standard Frame Rate LCD Frame Freq: 23.3 (min) 73.1 (max)

1 (1): Fast Frame Rate (Standard Frame Rate x2) LCD Frame Freq: 46.6 (min) 146.2 (max)

Selects the alternate clock source

0 (0): Select Alternate Clock Source 1 (default)

1 (1): Select Alternate Clock Source 2

LCD AlternateClock Divider

0 (0): Divide factor = 1 (No divide)

1 (1): Divide factor = 8

2 (10): Divide factor = 64

3 (11): Divide factor = 512

LCD Fault Detection Complete Interrupt Enable

0 (0): No interrupt request is generated by this event.

1 (1): When a fault is detected and FDCF bit is set, this event causes an interrupt request.

Pad Safe State Enable

0 (0): LCD frontplane and backplane functions enabled according to other LCD control bits

1 (1): LCD frontplane and backplane functions disabled

Voltage Supply Control

0 (0): Drive VLL3 internally from VDD

1 (1): Drive VLL3 externally from VDD or drive VLL internally from vIREG

Load Adjust

Charge Pump or Resistor Bias Select

0 (0): LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.)

1 (1): LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.)

Regulated Voltage Trim

Regulated Voltage Enable

0 (0): Regulated voltage disabled.

1 (1): Regulated voltage enabled.